1. Field of the Invention
The present invention relates to a data recovery method and a data recovery circuit for restoring serially transmitted data.
2. Description of Related Art
In recent years and continuing, various types of high-speed interface standards have been proposed and put into practical use in order to respond to demand for high-speed data transmission. Examples of such interface standards include USB (Universal Serial Bus), Serial ATA (Advanced Technology Attachment), IEEE 1394, 1G/10G Ethernet (Registered trademark), InfiniBand, RapidIO, Fibre Channel, and PCI (Peripheral Component Interconnect bus) Express. It is expected that more and more emphasis will bw put on higher-rate and large-capacity data communication in the future.
Most of the high-speed interfaces employ serial transmission schemes for transmitting data according to a predetermined frequency. A clock of that frequency is embedded in the transmitted data. The receiving end extracts this clock from the received data, and restores the received data based on the extracted clock signal. The circuit for conducting the restoration process is called a clock data recovery (CDR) circuit.
In conventional CDR circuits, a phase locked loop (PLL) is generally used. The oscillation signal (or the clock) of the voltage controlled oscillator (VCO) of the PLL is controlled so as to be synchronized with the phase of the received data. The oscillation signal is output as a reproducing clock signal. The received signal is latched using the reproducing clock signal as the reference, and accordingly, restored accurately.
However, along with every year's increase of data transmission rate, the VCO frequency has reached the GHz order for data transmission. The CDR circuit incorporating such a high-frequency VCO has some negative effects, including increased chip size, increased power consumption, and increased cost. In addition, wiring-induced clock delay cannot be ignored in such a situation where further speed-up of data transmission is required, and sufficient consideration has to be given to wiring layout and device arrangement. As a result, the circuit design becomes more complicated. Since wiring delay greatly depends on the characteristics of the employed tools or devices, the wiring layout may have to be redesigned for each process, and in the worst case, the circuit itself may have to be redesigned. Thus, the reusability of the circuit is degraded, and the development period becomes long.
To overcome the above-described problem, an oversampling data recovery circuit is proposed. See B. Kim et al., “A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-um CMOS” IEEE JSSC, December 1990, at 1385-1394.
FIG. 1 is a schematic block diagram illustrating the structure of a conventional clock data recovery (CDR) circuit. The conventional CDR circuit includes a multiphase clock generator 200, a flip flop circuit 201, and a digital PLL (DPLL) 202. The multiphase clock generator 200 is structured by a phase locked loop (PLL) or a delayed locked loop (DLL), and generates multiple clocks with the phases shifted from the reference clock (RefCLK) at regular intervals.
The flip flop (F/F) circuit 201 includes multiple flip flops, each of which receives input data at the data input terminal via a common path and receives a clock (one of clocks CLK1-CLKN) at the clock input terminal. Each flip flop takes the input data in at the rising edge (or the falling edge) of the corresponding clock. Accordingly, the data output from the flip flop circuit 201 are a set of data items sampled at the phase-shifted clocks. The digital PLL 202 detects the logic inversion timing from the bit sequence supplied from the flip flop circuit 201, selects a clock in sync with the inversion timing from the multiple clocks, and restores the selected clock as a recovery clock (Rec CLK). The DPLL 202 also selects and outputs data that have been sampled at a clock with the phase shifted (e.g., a clock in opposite phase) from the recovery clock (for example, a clock in opposite phase), as recovery data (RecData). The data inversion timing is detected after filtering (or smoothing by a filter) to select the recovery clock (RecCLK). This recovery clock (RecCLK) is used in the later-stage signal processor. With this arrangement, all the circuits, except for the multiphase generator 200, can be structured by digital circuits, and easily implemented.
However, the phase difference among the multiple clocks has to be controlled precisely because uneven phase difference may introduce errors.
FIG. 2 is a timing chart showing the problem caused by variation in phase difference in the conventional clock data recovery circuit. In this example, four clocks (CLK1-CLKN4) are generated with the phase shifted by prescribed degrees. It is assumed that the phase of CLK2 is behind from the ideal state by Δ, that CLK2 is selected as the recovery clock (RecCLK), and that each data set is processed in sync with the recovery clock in the signal processor. If the phase of the recovery clock (RecCLK) is switched to that of CLK 1 at time Tsw, the period (T′) of the recovery clock (RecCLK) becomes shorter by Δ, other than the original phase difference. Consequently, time Tsu′ required to set up the flip flop in the signal processor cannot be guaranteed, and in the worst case, errors occur. Even if the circuit is designed such that the clocks are generated at regular intervals at the output terminals of the multiphase clock generator 200, these clocks are influenced by skew (due to, for example, wiring or load) before the recovery clock (RecCLK) output terminal. The skew becomes conspicuous as the operating speed increases. In this case, variation in delay among multiple clocks has to be eliminated at each site; however, such elimination is very difficult and has not been realized yet.
Another publication JP 2002-190724A discloses a phase control technique for adjusting the clock phase using a phase interpolator at the multiphase clock generator. Using a phase interpolator enables multiple clocks to be output with the phase shifted at strict regular intervals. However, the circuit scale becomes large, and the wiring delay due to high-speed operation cannot be ignored. The wiring delay could be avoided by correcting the phases of the multiple clocks every input stage; however, this method is as difficult as implementing an oversampling CDR circuit that operates at oversampling frequency (which is four times the clock frequency of the transmitted data in the example shown in FIG. 2).
Thus, for those apparatuses using a conventional CDR circuit with an analog PLL or an oversampling CDR circuit to recover the clock from the input data to conduct signal processing based on the recovered clock, the development period becomes longer and longer as the transmission rate increases because CDR design becomes more difficult.